The present invention relates to semiconductor devices and, more particularly, to a method for manufacturing a semiconductor device having a resistance circuit and a non-volatile memory.
FIG. 5 and FIG. 6 show sectional views of a conventional semiconductor device. In FIG. 5, an electrically erasable programmable read only memory (hereinafter abbreviated as EEPROM) and a resistance body are structured by one layer of polysilicon. In FIG. 6, an EEPROM is structured by one layer of polysilicon and a resistance body is structured by a diffusion layer.
In the above-described conventional semiconductor device, the EEPROM is structured by one layer of polysilicon. In particular, because its control gate is formed by a diffusion layer, there is defect that the cell size is large and high integration is difficult. Also, where the resistance body is structured by polysilicon as in FIG. 5, this polysilicon serves also as a gate electrode of the MOS transistor so that the film thickness is comparatively thick of from 3000 Angstroms to 5000 Angstroms. Accordingly, there is defect that it is difficult to increase the resistance while keeping high accuracy. Also, where the resistance body is structured by a diffusion layer as in FIG. 6, the parasitic capacitance between it and the substrate is greater in comparison with the case of the polysilicon. Further, the voltage applied to the resistance body varies the extension of a depletion layer width toward the diffusion layer, and there is a problem that the resistance value possesses voltage dependency.
It is an object of the present invention to eliminate the above-stated problem and provide a manufacturing method to form at the same time an EEPROM small in cell size and a resistance body with accuracy and stability on a same substrate.